A multiplying digital-to-analog (D/A) converter is used in, for example, a cyclic A/D converter and each stage of a pipeline A/D converter. In a multiplying D/A converter disclosed in U.S. Pat. No. 7,397,287 corresponding to JP-A-2007-159087, an input voltage is subtracted by a reference voltage and then doubled. Then, a residue voltage is generated by subtracting a voltage depending on an A/D conversion value of the input voltage from the doubled voltage.
A single-ended input sample and hold circuit used in the multiplying D/A converter disclosed in U.S. Pat. No. 7,397,287 is constructed with an operational amplifier (op-amp), inverting-side capacitors connected to an inverting input terminal of the op-amp, and non-inverting-side capacitors paired with the inverting-side capacitors and connected to a non-inverting input terminal of the op-amp. In a sampling phase, at least one capacitor is charged by the input voltage, and each of the other capacitors is charged by a predetermined voltage. In a holding phase, the inverting-side and non-inverting-side capacitors of at least one capacitor pair are respectively connected between input and output terminals of the op-amp, and the input voltage is applied to at least one capacitor.
In the sample and hold circuit disclosed in U.S. Pat. No. 7,397,287, when predetermined conditions are met, an input voltage (i.e., common mode input voltage) of the op-amp in the holding phase does not depend on the input voltage of the op-amp in the sampling phase, and the sampled voltage accurately remains held even when the input voltage changes in the holding phase. In this way, the op-amp is supplied with a sufficient common mode input voltage that allows the op-amp to work at a desired gain and slew rate. In the sample and hold circuit and the multiplying D/A converter disclosed in U.S. Pat. No. 7,397,287, the input voltage range (input dynamic range) is limited to from 0 volts (V) to a power supply voltage. Therefore, for example, when the multiplying D/A converter is used in the initial stage of the pipeline A/D converter, a voltage outside the input voltage range cannot be inputted.
An A/D converter disclosed in JP-A-2006-024975 and U.S. Pat. No. 7,312,733 corresponding to JP-A-2006-115027 is configured to process a voltage outside an input voltage range. In the A/D converter disclosed in JP-A-2006-024975, an input voltage is divided by a voltage divider and then inputted to an A/D conversion section. In the A/D converter disclosed in U.S. Pat. No. 7,312,733, when it is detected that an A/D conversion value reaches the maximum or minimum value representable by A/D conversion bits, a bias voltage of an amplification circuit is switched by a bias control circuit to shift an output voltage of the amplifier circuit. An outputted digital value is corrected by correction data depending on the bias voltage.
As disclosed in JP-A-2006-024975 and U.S. Pat. No. 7,312,733, the input voltage range may be increased by using a voltage divider constructed with resistors or a bias control circuit. However, the addition of the voltage divider or the bias control circuit may result in a reduction in accuracy of A/D conversion, an increase in size, and an increase in the number of parts.